1. Field of the Invention
This invention relates generally to electronic circuits and more particularly to data buffering of signals between two clock domains using a First In, First Out (FIFO) hierarchy.
2. Description of the Related Art
Many data processing and communication devices, such as computer networks, require communication between elements operating at different frequencies. One problem with such asynchronous communication is that data transmission between the data write element and the data read element must be controlled carefully to prevent data loss or spurious transfers. If the data write element transmits data faster than the data read element can receive, information may be lost. Alternately, if the data receive element accepts information faster than the data write element can transmit, the same data may be received twice.
A First In, First Out (FIFO) buffer is commonly used between such elements. During operation of a FIFO, a first component writes data to the FIFO buffer and a second component reads from the FIFO buffer. Each component reads or writes according to its own clock frequency. As two separate components with separate frequencies control read and write operation timing, the buffer is operated in an asynchronous manner, and time separation between read and write operations may be very short.
The problem between in buffering data is that buffers have finite size. If the data write element operates faster than the data read element for an extended period of time, the buffer may overflow, thereby causing data loss. If the data read element operates at a faster rate, the buffer may empty and the data read element may receive invalid data.
It is difficult to regulate the fill status of the data buffer and compensate for data loss and spurious transmission problems. A need therefore exists to monitor and maintain the fill status of the FIFO buffer in a manner that minimizes errors common in asynchronous systems.
It is therefore an object of the current invention to provide a reliable system for transmitting data at an asynchronous rate by minimizing data loss and spurious data transmissions.
It is another object of the current invention to improve the traditional data buffering FIFO scheme by providing a system which is stable and fill status flags which are reliable.